4 bit 3 bit binary multiplier
Weill, Seal Beach, both of Calif. This multiplier generates the binary product of any two 4-bit binary numbers such that the input signals propagate serially through at most only three logic gating cell stages. An extension of the multipliers basic logic partition scheme permits design of larger multipliers in which adders and 4X 4-bit multipliersare used as building blocks.
A detailed 8 X 8-bit multiplier design is presented to concretely describe the approach. The Zs-complement 4 X 4-bit multipliers-logic partition is almost identical to the one used 4 bit 3 bit binary multiplier the all positive 4 X 4-bit multiplier design, incorporating subfunctions which are nearly all identical to their counterparts in the all positive multiplier.
The propagation delay and power dissipation for this multiplier would depend on how the array was built. To compare it fairly with LSI, it is assumed that Motorola chips are assembled in a hybrid package reducing cable delay between parts and reducing termination power 4 bit 3 bit binary multiplier.
In this case the multiplier delay would 4 bit 3 bit binary multiplier between about 24 and 32 nanoseconds and 4 bit 3 bit binary multiplier power dissipation would vary between 2. By way of contrast, the 4 X 4-bit multiplier design described in this application would 4 bit 3 bit binary multiplier between 7 and 8 nanoseconds delay and consume about 3 watts if its cascode cell circuitry were fabricated on a similar production line.
L81 4 X 4-Bit Multiplier Special multiplier arrays'built using special cells and LSI or hybrid connected can also be contrasted with the design disclosed here. Breuer et a], Interim Technical Report, Julypp. It is built by interconnecting 16 identical cells, each of which contains 2, 3-level, specially tailored cascode circuits. That report discloses both the multiplier logic design, and schematic diagram for each identical call. Even though this multiplier uses a logically more poserful 4 bit 3 bit binary multiplier cascode cell which is moreover custom designed for use in just this multiplier circuit, it subtends a nominal 28 ns delay.
4 bit 3 bit binary multiplier is because its logic design requires signal path propagation through a seven stage delay cell interconnection. The circuit dissipates about 1 watt its relatively small good power delay product is achieved because the cell array has apparently been fabricated in a very high quality IC line. This is the case because higher speed components can be operated at a higher data rate words or operations per second and therefore fewer high speed components can be used to replace several of their conventional counterparts.
In signal processors, multipliers are particularly important. They are used in fairly large numbers in the range focusing. Accordingly, it is a first object of the present invention to provide a 4 X 4-bit binary multiplier module having a higher speed than that available from prior art components. It 4 bit 3 bit binary multiplier a second object of the present invention to provide a multiplier module capable of expansion into larger multipliers.
It is a third object of the present invention to provide a 4 bit 3 bit binary multiplier logic design which simplifies implementation of the multiplier using universal logic blocks. It is a fourth object of the present invention to provide a 4 X 4-bit binary multiplier requiring the input signal to propagate serially through at most only 3 logic gating stages. A specific object of the present invention is to provide for a multiplier logic design capable of implementation using the logic building blocks of a type known as Modular Unit Delay 4 bit 3 bit binary multiplier Logic Gates.
Devendorf, entitled Universal Logic Gate, Ser. A special 6 by 4 bit adder is responsive to signals representative of selected digits of partial products S and T and generates intermediate variables at a first stage and then at the second stage forms from these intermediate variables the three most significant output digits.
The multiplier module of the present invention referred to briefly above and described in greater detail below permits the performance of binary multiplication operations at between 2 and 3 times faster and with smaller attendant multiplier hardware costs than any other comparable multipliers available, depending on the type of integrated circuit processing 4 bit 3 bit binary multiplier. If the circuits were to be fabricated processed using an up-to-date, high performance IC processing technique, the multiplier would probably have between 7 and 8 nanoseconds delay and the power dissipation of the circuit would be about 3.
Therefore, a multiplication rate of greater than 4 bit 3 bit binary multiplier per second would be possible. These performance figures contrast favorably with those of the other comparable multipliers described above.
Accordingly, given the availability of unit delay ULGs, the multiplier logic design of the present invention may specify a 3-stage network of small logic blocks and the logic function to be performed by each is based on Boolean algebra and the numerical properties of binary multiplication. The logic design thus derived is then refined and tailored to make fuller use of cascode cell logic synthesis capabilities.
The cells can frequently mechanize functions of more than four input variables while subject to the same interconnection restrictions as in 4-input ULG synthesis, thereby implementing the larger functions in the same one stage ULG delay. Development of Logic Partitions for a 3-Stage 4 X 4-bit Binary Multiplier The foundation of the 4 X 4-bit multiplier logic design is the decomposition of its 4 X 4-bit multiplication operation into two 2 X 4-bit multiplications.
The products 4 bit 3 bit binary multiplier in these component multiplications feed a 6 X 4-bit adder whose output sum array comprises the 6 most significant multiplier output bits. The multiplier binary inputs with each a, or a, l and b, 0 or b l are expressed as and N, 0,2 11 2 1,2 a 1 ,2 17 2 0 2" 1 2 1,2 a 17,2 b. In the last equation, the product, N is 4 bit 3 bit binary multiplier as the sum of the products formed in two component 2 X 4-bit multiplications in which the first 2 X 4-bit product is weighted by 2 before it is added to the second.
A graphical delineation of operations performed when the 4 X 4-bit multiplication implements this latter expression is as follows:.
The graphical presentation above schematically 4 bit 3 bit binary multiplier a logic partition for a 3-stage 4 X 4-bit binary multiplier synthesis which serves as a starting point in its design.
In that partition, two parallel one-stage logic block arrays synthesize the coefficients in S and in T. The S and S, S-coefficients are the coefficients C and C, in the expansion for N N, N and are therefore output from the multiplier, as they are at the S-array logic block outputs. The remaining S-coefficients and all of the T- coefficients are fed to a two stage array which implements a 6 X 4-bit addition in a modified version of a 4-bit Adder as shown in FIG.
In that and subsequent FIGS, the following symbols are used to represent the designated gates:. Furthermore, it should be no ted tha t L is formed by means of a wired OR from X and X The output C from portion 24 of block '24 is given by:. The coefficients C C C C are the 3rd through 6th multiplier output bits. The remaining operation performed in the 6 X 4 bit adder is equivalent to that of adding the number C2 produced in the first addition to the number I T 2 T 2 defined by the remaining T coefficients input to the adder.
The sum t C2 encodes the last two of the 4 X 4-bit multiplier outputs. Thus, only two stages are required, as would be true of a 4 X 4-bit adder. Since several different kinds of circuitry, other than cascode cells might be used to implement the logic function specified for each box, FIG.
The logic design shown in FIG. However, it should be noted in 4 bit 3 bit binary multiplier. But as will become more clear hereinafter, in the specific embodiment shown in FIG. Therefore, T and S are never observable logic signals. The completion of T occurs within a third level logic block cells and of FIG.
The first type of refinement involved utilization of special properties relating to some of the S and T,- functions.
Since cells can generate OR functions more economically than parity functions, the cell count required in the ULG is reduced. Because T a b i, it is not really necessary to generate T with the first level gate 41 as shown in FIG. Instead it can be generated internally from a b and T in the second level gate 30 of FIG. The second class of design simplifications involves making a broader, more general use of the cascode cell's 4 bit 3 bit binary multiplier capabilities.
In this and subsequent figures, X, Y, and Z defined respectively as:. It is noted there that output e. As explained in the above referenced co-pending application, such a connection prior to the load cells 47 and 48 is the logical equivalent of an AND gate, while such a connection following load cells is the equivalent of an OR gate. In some cases, two cell, l-stage syntheses of very complex functions such as 5 T and S arent possible without exceeding the collector-dotting limits imposed in 2-cell 4-variable function synthesis to limit delay.
In these cases partial functions 5, T and 8 are synthesized in 2-cell blocks and then each respective synthesis is completed at a succeeding stage which might otherwise not be used to its fullest capability. The synthesis of the function L, is shown in FIG.
After several simplifications of the types discussed above, the final design of FIG. There, each block is a 2-level cascode cell and the entire design is implemented in 3 stage delays by the cell array. It is noted in particular that the 5-variable fundtions S and T as well as the 6-variable functions 3 and T are each realized in 2cell blocks, indicated by reference numerals 61, 62, 63, and 64 respectively. The cell collector and load cell interconnections there are precisely those used most frequently in 4-variable function synthesis.
In the figure, each box signifies a cascode cell circuit. The numbers in the smaller boxes along the inside vertical edges of each cell symbol designate the bonding pad numbers for the individual cell IC dies. This numbering would be different if a different IC cell layout format were used. The letters of block 1 15, however, identify the cell inputs X,Y,Z and output current nodes A,B,C,D and the arrows identify load cell input and output nodes.
These functional designations are the same for all cells in the figure and are defined in greater detail in the above referenced Universal Logic Gate" Application. Consequently, the wiring diagram of FIG. Outputs from the first row of cells through whose inputs are entirely comprised of the multiplier input signals, are fed to cells in the second and third rows or generate multiplier outputs directly cells and Inputs to the second row of cells through are either multiplier input signals or are derived only from outputs from cells in the first row.
Cell 1 16 produces the third multiplier output bit and all other outputs from cells in the second row drive third r ow cells through Multiplier inputs H and b feed cell along with signals produced in the second row. Otherwise, cells in the third row are fed exclusively by signals output from cells in the first and second rows. All remaining multiplier output signals are produced by cells in the third row. In no case is any output from a cell in any row fed to an input of another cell in the same or higher row constant programming signals are fed to cells1 l8, and from load cell outputs from other cells in the same row, however.
Consequently, the cells are interconnected in a feed forward only manner and therefore the multiplication delay is that subtended by only 3-cell-stages. Logic Design of a 3-Stage 3 X 4-bit 2s Complement Binary Multiplier 4 bit 3 bit binary multiplier same techniques employed in the design of the 3 stage, 4 X 4-bit all positive binary multiplier described in detail above, can be used to design a 3-stage 4 X 4-bit 2s complement multiplier FIG. The mathematical 4 bit 3 bit binary multiplier partition approach is identical and the resulting design utilizes nearly the same hardware configuration for two reasons.
First, as is well known, the 4 least significant output bit functions are identical to those of the all positive multiplier. Second, most of the internally generated S and T functions are the same, also. Moreover, the two most significant output bits of the 2s complement multiplier, while different functions from those in the all positive multiplier, are actually easier to generate than their counterparts.
The foundation of the 4 X 4-bit twos complement multiplier design is the decomposition of the 4 X 4-bit multiplication operation into two 2 X 4-bit multiplications. The products formed in these component multiplications feed a 4-bit modified adder whose output sum array comprises the central four of the eight multiplier output bits.
The two least significant and the two most significant output bits are generated directly by relatively simple logic and are not outputs of the adder. Note that a and b;, are each preceded by a negative sign so that the first term of each expression has a value of either O or 8.
The product N, N N defined by added to the second. A graphical delineation of operations performed when the 4 X 4-bit multiplication implements this expression is as follows:.
The adder 71 used in this embodiment is a modified 4-bit adder in the following two respects: First, 5, has negative weight thus subtracting from the sum instead of adding and second, the last carry or borrow is ignored because it affects only C, and C which are generated separately.
The equations for the output bits 4 bit 3 bit binary multiplier the modified adder are shown in Table 2 and its logic synthesis 4 bit 3 bit binary multiplier within the dashed area 71 of FIG. A two-stage, eight-cell synthesis is made possible by using wired-logic 72 to synthesize the last exclusive OR operation in the generation of C It differs from the adder FIG.
Note that T's coefficient array is shifted two places to the left relative to the S array since T is multiplied by 2 and that S and T, carry negative weights in the summands S and 2 T.
A binary multiplier is an electronic circuit used in digital electronicssuch as a computerto multiply two binary numbers. It is built using binary adders. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial productsand then summing the partial products together. This process is similar to the method taught to primary schoolchildren for conducting long 4 bit 3 bit binary multiplier on base integers, but has been modified here for application to a base-2 binary numeral system.
Between Arthur Alec Robinson worked for English Electric Ltd, as a student apprentice, and then as a development engineer. Crucially during this period he studied for a PhD degree at the University of Manchester, where he worked on the design of the hardware multiplier for the early Mark 1 computer.
Mainframe computers had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine". Early microprocessors 4 bit 3 bit binary multiplier had no multiply instruction.
Though the multiply instruction is usually associated with the bit microprocessor generation,  at least two "enhanced" 8-bit micro have a multiply instruction: As more transistors per chip became available due to larger-scale integration, it became 4 bit 3 bit binary multiplier to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time.
Because some common digital signal processing algorithms spend most of their time multiplying, digital signal processor designers sacrifice a lot of chip area in order to make the multiply as fast as 4 bit 3 bit binary multiplier a single-cycle multiply—accumulate unit often used up most of the chip area of early DSPs. The method taught in school for multiplying decimal numbers is based on calculating partial products, shifting them to the left and then adding them together.
The most difficult part is to obtain the partial products, as that involves multiplying a long number by one digit 4 bit 3 bit binary multiplier 0 to A binary computer does exactly the same, but with binary numbers. In binary encoding each long number is multiplied by one digit either 0 or 1and that is much easier than in decimal, as the product by 0 or 4 bit 3 bit binary multiplier is just 0 or the same number.
Therefore, the multiplication of two binary numbers comes down to calculating partial products which are 0 or the first numbershifting them left, and then adding them together a binary addition, of course:. This is much simpler 4 bit 3 bit binary multiplier in the decimal system, as there is no table of multiplication to remember: This method is mathematically correct and has the advantage that a small CPU may perform the multiplication by using the shift and add features of its arithmetic logic unit rather than a specialized circuit.
The method is slow, however, as it involves many intermediate additions. These additions take a lot of time. Faster multipliers may be engineered in order to do fewer additions; a modern processor can multiply two bit numbers with 6 additions rather than 64and 4 bit 3 bit binary multiplier do several steps in parallel.
Modern computers embed the sign of the number in the number itself, usually in the two's complement representation. That forces the multiplication process to be adapted to handle two's complement numbers, and that complicates the process a bit more.
Similarly, processors that use ones' complementsign-and-magnitudeIEEE or other binary representations require specific adjustments to the multiplication process. For example, suppose we want to multiply two unsigned eight bit integers together: We can produce eight partial products by performing eight one-bit multiplications, one for each bit in multiplicand a:. In other words, P [ If b had been a signed integer instead of an unsigned integer, then the partial products would need to have been sign-extended up to the width of the product before summing.
If a had been a signed integer, then partial product p7 would need to be subtracted from the final sum, rather than 4 bit 3 bit binary multiplier to it. The above array multiplier can be modified to support two's complement notation signed numbers by inverting several of the product terms and inserting a one to the left of the first partial product term:.
There are a lot of simplifications in the bit array above that are not shown and are not obvious. The sequences of one complemented bit followed by noncomplemented bits are implementing a two's complement trick to avoid sign extension.
The sequence of p7 noncomplemented bit followed by all complemented bits 4 bit 3 bit binary multiplier because we're subtracting this term so they were all negated to start out with and a 1 was added in the least significant position.
For both types of sequences, the last bit is flipped and an implicit -1 should be added directly below the MSB. For an explanation and proof of why flipping the MSB saves us the sign extension, see a computer arithmetic book. Older multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area.
Modern multiplier architectures use the Baugh—Wooley algorithmWallace treesor Dadda multipliers to add the partial products together in a single cycle.
The performance of the Wallace tree implementation is sometimes improved by modified Booth encoding one of the two multiplicands, which reduces the number of partial products that must be summed. From Wikipedia, the free encyclopedia. Fundamentals of Digital Logic and Microcomputer Design. Architecture, Programming and System Design, Retrieved from " https: Digital circuits Binary arithmetic Multiplication. All articles with unsourced statements Articles with unsourced statements from August Views Read Edit View history.